The invention relates to a circuit arrangement for the EXCLUSIVE-OR linkage of two signals.
U.S. Pat. No. 4,408,134 discloses an XOR gate using ECL [emitter coupled logic] technology in which two inputs A and B are connected with the base terminals of current switching transistors in of superposed pairs of current switches (21, 24 and 25 in FIG. 2 of the patent). The bases of the respective other current switching transistors (22, 23 and 26) are connected with internal reference voltage sources (V.sub.BB1 and V.sub.BB2, respectively). The collector currents of transistors 21 and 23 flow through a common load resistance element 28 at which a voltage signal is dropped that represents the EXCLUSIVE-OR linkage of the signals present at inputs A and B. This output signal travels via an emitter follower 27 to the output node 17 of the XOR gate.
An improved circuit arrangement for the EXCLUSIVE-OR linkage of two signals is shown in FIG. 1. This arrangement is configured in emitter-emitter coupled logic (ECL) technology. But this improved arrangement also has some drawbacks. In order to make these drawbacks clearer in the discussion below, brief reference will be made to the purpose of the individual function blocks.
A first input stage for input signal U.sub.E1 is composed of input transistors EF.sub.1 and EF.sub.2 as emitter followers. A second input stage for input signal U.sub.E2 includes two input transistors EF.sub.3 and EF.sub.4, each connected, at a diode D.sub.1 and D.sub.2 , respectively, to an emitter follower EF.sub.7 and EF.sub.8, respectively. The input stages serve for level matching as well as decoupling of the actual XOR gate from the enabling or driving circuit. The transistors of the input stages each have their collectors connected to ground and, by way of their emitter resistances R.sub.2, R.sub.3 and R.sub.4, to the negative pole of an operating voltage source U.sub.B. The actual XOR gate is composed of current switches which are superposed on one another (series gating). Because of this serial connection, a shift in level is necessary between the two input signals of the actual XOR gate. This is accomplished by the pair of diodes D.sub.1, D.sub.2 and a pair of emitter followers EF.sub.7 and EF.sub.8. In the illustrated embodiment, the potential difference between the two internal signal planes is thus twice the base-emitter voltage.
The mentioned current switches including transistors T.sub.1 to T.sub.6 serve to establish a logic linkage of the two input signals. The lower pair of current switches including transistors T.sub.5 and T.sub.6 are coupled together at their emitters and connected via a current source I.sub.O with the negative pole of the operating voltage source U.sub.B. The base inputs are enabled or driven by the outputs of emitter followers EF.sub.7 and EF.sub.8, respectively. An upper pair of further current switches is connected to each one of the two collector outputs i.sub.5 and i.sub.6. The two base inputs of the first pair T.sub.1, T.sub.2 are enabled or driven by the emitter outputs of the first input stage EF.sub.1 and EF.sub.2, respectively, while the base inputs of the second pair T.sub.3, T.sub.4 are enabled inversely thereto by the emitter outputs of the same mentioned input stage. The four collector outputs of the two upper current switch pairs are connected in parallel by pairs, i.sub.1 with i.sub.3 and i.sub.2 with i.sub.4, and are each connected via load resistance elements R.sub.1 with ground potential (positive potential) of the operating voltage source U.sub.B. The difference output signal can be picked up at these load resistance elements R.sub.1. In order to regenerate the signal levels and to decouple the actual XOR gate from the output, a buffer stage is provided subsequently which, in the illustrated example, is composed of two pairs of emitter followers EF.sub.9, EF.sub.11 and EF.sub.10, EF.sub.12 having emitter resistances R.sub.5, R.sub.6 ; R.sub.5, R.sub.6 that are connected with the negative pole of the operating voltage source. The buffer stage is connected to a current switch including the likewise emitter-coupled transistors T.sub.8, T.sub.9 whose common emitter is connected, via a current source controlled by a control voltage U.sub.ref, with the negative pole of the operating voltage source U.sub.B. A transistor R.sub.10 and a resistor R.sub.7 are connected in series to provide the current source. The two collector outputs of T.sub.8 and T.sub.9 have external load resistances 2.times.R.sub.8 that are connected with ground potential.
If the signal level at one input of the XOR gate changes while the level at the other input remains constant, the voltage at the output of the XOR gate changes; if both input levels are switched simultaneously, the output signal of an ideal XOR circuit is not influenced. Since, however, during switching the difference voltage at the current switch inputs of both signal planes temporarily takes on a value of 0 volt, the current I.sub.O at this moment flows through the two load resistance elements R.sub.1 in equal parts. Thus the magnitude of the XOR output voltage is reduced before the original positive or negative maximum output voltage value is reestablished. In the most unfavorable case, the difference output voltage collapses to 0 volt.
The disadvantages of the XOR gate become evident in the following different applications.
1. Frequency Dependent Differences In Delay Between The Signal Planes
The logic linkage of the input signals takes place in transistors T.sub.1 to T.sub.4. The signals there flow over two different paths. While one input signal reaches the bases of T.sub.1 and T.sub.4 via emitter follower EF.sub.1 and the bases of T.sub.2 and T.sub.3 via EF.sub.2, respectively, the other input signal flows via EF.sub.3 /D.sub.1 /EF.sub.7 and T.sub.5 to the emitters of T.sub.1 /T.sub.2 and via EF.sub.4 /D.sub.2 /EF.sub.8 and T.sub.6 to the emitters of T.sub.3 /T.sub.4. Due to the finite switching speed of the transistors, the delay on the different signal paths becomes different.
Thus, a delay difference t.sub.L results between the signals to be linked which, in the different possible uses of the XOR gates, has the following effect:
1.1 For frequency doubling, periodic signals having merely a suitable phase difference are applied to the two inputs of the XOR gate, for example: EQU u.sub.E1 =U.sub.1 .multidot.sin .omega.t EQU u.sub.E2 =U.sub.1 .multidot.sin .vertline..omega.t-.phi..vertline..
The differences in delay of the input signals as a result of the different signal paths in the XOR gate can be described by an additional phase angle .xi. between the input signals if one wishes to consider the XOR gate to be ideal with reference to differences in delay. Since, however, the difference in delay is also a function of the circuit frequency, .xi.=f (.omega.). If EQU .phi.-.xi.(.omega.=(2n-1).multidot..pi./2
the XOR gate exhibits the ideal behavior during frequency doubling. Only in this case is the output signal of the XOR gate free of direct voltage so that the desired keying ratio of 1:1 results. Thus, in order to realize optimum operation of the gate as a frequency doubler, the phase angle .phi. between the input signals must be set as a function of the operating frequency. This, however, is hardly possible, particularly if the enabling circuits are monolithically integrated.
1.2 Differentiating and Rectifying
For differentiating and rectifying any desired bit sequence is fed directly to one XOR input and the same bit sequence is fed with a delay to the other XOR input. The output signal level thus changes for each edge of the input signal so that clock recovery from the bit sequence is possible. In this use, the described XOR gate has the following drawbacks. The ascending edge and the descending edge of the output signal have different edge steepnesses since the signal paths to the upper and lower current switching plane exhibit different lowpass behavior. The curve shape of the output signal may thus become asymmetrical and depends on which signal plane is enabled directly and which with a delay.
1.3 Use as Phase Detector
If one enables the XOR gate as described above in subsection 1.1, the output direct voltage is a measure for the phase shift between the two input clock signals: EQU u.sub.A -=U.sub.A,O .multidot.cos.multidot..vertline..phi.-.xi.(.omega.).vertline..
The maximum sensitivity, u.sub.A- /d.phi., occurs for .phi.-.pi./2+.xi.(.omega.). Because of the frequency dependent difference in delay, the point of symmetry of the function u.sub.A- =f(.omega.) is also frequency dependent.
1.4 Logic Linkage of Bit Sequences
If one places any desired bit sequences at the two XOR inputs, the XOR output voltage is permitted to change its level if only one of the two input voltages changes. The difference .DELTA.t.sub.L in delay between the different signal paths as already defined in section 1 results in a corresponding jitter in the output signal which, due to the frequency dependency, cannot be compensated over a broad band.
As discussed in subsection 1.2, the edge steepness of the output signal may additionally be dependent on the current switching plane in which the switching takes place.
2. Input Impedance
Due to the asymmetry of the circuit, the two XOR inputs have different input impedances. As a result of this, the input signal sources are subjected to different loads. Moreover, the reflection factors of the two inputs differ.